Chennai: IIT Madras and IIT-M Pravartak Technologies Foundation are calling for registration from students, industry professionals and researchers to take part in the ‘Digital India RISC-V’ Symposium, a one-day event showcasing ‘The future of Electronics in India through the RISC-V pathway.’ It is scheduled to be held in August at IIT Madras Research Park in Taramani here.  

This is a platform to gain insights into the growing RISC-V ecosystem in India. The event has limited seats. Registration and participation are free of cost. Registrations are open for the symposium. Interested can register through the following link - https://pravartak.org.in/dirv_tech_confluence_registration.

Rajeev Chandrasekhar, Minister of State for the Ministries of Electronics and Information Technology and Skill Development and Entrepreneurship, and Prof. V. Kamakoti, Director, IIT Madras, who developed ‘SHAKTI,’ India’s first indigenously designed microprocessor based on RISC-V ISA, are scheduled to address the event along with other eminent dignitaries.

This Symposium will feature insightful tech talks by esteemed academicians, industry experts, interactive stalls showcasing indigenous RISC-V processors, an engaging hackathon conclusion, and a special investor session.

‘RISC’ stands for ‘Reduced Instruction Set Computer’ contrasted against other prevalent architecture, ‘CISC’ (Complex Instruction Set Computer), ‘V’ stands for fifth generation. The RISC-V project began in 2010. The RISC-V ISA enables a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA aims to deliver a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

The RISC-V foundation was formed in 2015 with IIT Madras being one of the founder members.

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